| -compat <type> | define language compatibilities - not all Verilog®
implementations are exactly the same - this flag allows you
to make vcomp compile to a language closer to a particular
dialect - see the section on
Comparative Implementations
for more detaiuls
- default - same as '-compat ansix'
- ansi - ANSI 1.0 Verilog®
- ansix - ANSI 1.0 Verilog® - with == 'fixed'
- vcs - more like VCS®
- verilog - more like Cadence® Verilog®
|
| -cleanz | when enabled 'cleans' Z values when assigned register to register (converts them to Xs)
this is a non ansi-compatible vcomp feature sometimes helpful in tracking down
obscure bugs |
| -D | enables warnings about automatic creation of default nets |
| -e <name> | specifies an entry point for the compiled image should your
PLI program wish to take control before the main verilog® simulation |
| -f <file> | extends the command line into a script file - such files can define
symbols, specify files and libraries to read just like a normal command line |
| -F <file> | similar to -f except that the directory of the file specified becomes the default directory for files referenced within the script file |
| -h | prints a list of flags |
| -hierarchy | the compiler will produce a dump of the instance hierarchy to its
standard output as part of its normal running |
| -l <lib> | similar to the -l flag you pass to a C compiler to specify extra
object libraries to link against - you may need this if you are adding PLIs |
| -logfile <file> | copies all compiler messages to the specified file |
| -L <file> | specifies a file describing source library mappings |
| -LL <directory> | pass a directory for object library searching to the linker (use with -l above) |
| -o <file> | specify the name of the output file - by default if you don't present a '-o' directive the resulting file will be called 'vrun' |
| -O <num> | sets the 'optimization' level to <num> see
the description here for more information |
| -P <file> | specify the name of a PLI table file describing new PLI routines that
are being added to the compile-time environment - see the section on
PLI routines for more information. |
| -R | runs the program after compilation |
| -stacksize <bytes> | vcomp is carefull to use the smallest memory
footprint as possible - but for a very small number of Verilog® constructs it is not able to
determine the amount of memory space to allocate - one of these is the amount of stack space for
needed for recursive
function and task calls - neither of these constructs is actually particularly usefull in Verilog®
(due to the static nature of their parameters). If you do create a recursive subroutine call
vcomp allocates a fixed amount of stack space for it - by default it is 4k bytes but you can increase
it with the -stacksize directive |
| -v <libraryfile> | specifies a source library file - the only difference between a
library file and any other file is that modules declared in a library file are
only included in the final compilation if they are referenced by other modules
that are included |
| -v+<libraryname> <libraryfile> | specifies a source library file and maps it to a specific source library called <libraryname> - this option overrides anything specified in a -L library mapping file or a lib.map file - refer to Configuration Management for more information |
| -V | prints out the current version number of the compiler |
| -w | disables most warning messages |
| -y <directory> | specifies the directories that are searched for the files
named with -v directives |
| +acc | forces acc_* routine compiled-in support - this flag is rather a blunt tool
for what should be a careful job (if you want a fast running simulation) - it is more
precisely implemented with careful use of the -P PLI tables
- +acc+1 - equivalent to 'acc+=read,force,read_write'
- +acc+2 - equivalent to 'acc+=read,force,read_write,callback:*,callback_all:*'
- +acc+3 - equivalent to 'acc+=read,force,read_write,callback:*,callback_all:*,mp,mip,mipd'
- +acc+4 - equivalent to 'acc+=read,force,read_write,callback:*,callback_all:*,mp,mip,mipd,tchk,gate'
- +acc+ - same as +acc+1
|
| +define+<name>=<value>+ | defines a verilog® preprocessor <name>
to be defined to have the <value> - +define+<name>+ defines a name
with an empty value |
+incdir+<directory>
[+<directory>] | defines one or more directories
in which to search for files included with the `include compiler directive |
| +libext+<extension> [ +<extension> ] | defines one or more library extensions to search for |