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10. Optimization

This section deals with optimization options provided by the compiler. vcomp is an optimizing compiler - it automatically does many traditional compiler optimizations by default (constant folding, CSE, code scheduling, etc etc) as well as a number of Verilog® specific ones to do with reducing the number of events and keeping wires vectored where possible.

However it is also capable of performing many optimizations that may change the model you are simulating in simple, or more difficult ways - most of these optimizations can be disabled selectively.

The compiler flag '-O<n>' enables these optimizations <n> is a small integer, and if omitted is assumed to be '2'.

These optimizations come in two main flavors - ones that change the structure of simulation, and those that change the results of the simulation:

10.1 Structure changing optimizations

These classes of optimizations are enabled with '-O2' or just plain '-O'. By 'change the structure' of a simulation we mean that PLI routines would see a different structure - wires might be reported as regs, temporary variables might evaporate completely, modules may act as macromodules and be absorbed into the module that instantiates them - however the simulation itself should behave exactly the same way as if the optimization flag was not given.

Optimizations are named by the compile-time flags that disable them - when enabled with a -O2 flag the following optimizations are turned on, if the disabling flag follows the -O on the command line then that particular optimization is disabled:

  • -keep_wires - when enabled some wires are converted into registers and assign statements to them become always statements with register assignments
  • -no_merge_nets - when a net is simply assigned from another net and the assign is the only driver this optimization merges the two nets into the same object
  • -keep_gates - when enabled this optimization sometimes converts gates into always statements (they are no longer visible to PLI routines) and potentially merges those always statements together (note that disabling -keep_wires will usually negate any possibility of merging gates)
  • -keep_primitives - when enabled this optimization sometimes converts primitive instances into always statements and potentially merges those with other always statements

10.2 Behavior changing optimizations

This class of optimizations change the behavior of the simulation in a manner that may be tolerable to you - please read the list below carefully before you enable these with '-O4':

  • -keep_bufs - when enabled this optimization causes bufs with one output and one input that are driven by simple nets and drive simple nets to 'evaporate' and the two nets to be connected together as one - the behavior that changes is that a buf will pass a 1'bz input as 1'bx while the combined nets will pass the 1'bz unchanged.

10.3 Some notes on optimizations

For large designs it's worth experimenting with which optimizations you are using - don't assume that each individual optimzation will always make you simulation run faster - we've seen some counterintuitive results from simulations - especially with optimizations that remove nets - some nets can act as 'low pass filters' to 0-time glitches resulting in less rather then more event processing.

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